Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P–V–T fluctuations

Abstract

The leakage current, active power and delay characterizations of the dynamic dual Vt CMOS circuits in the presence of process, voltage, and temperature (P–V–T) fluctuations are analyzed based on multiple-parameter Monte Carlo method. It is demonstrated that failing to account for P–V–T fluctuations can result in significant reliability problems and inaccuracy in transistor-level performance estimation. It also indicates that under significant P–V–T fluctuations, dual Vt technique (DVT) is still highly effective to reduce the leakage current and active power for dynamic CMOS circuits, but it induces speed penalty. At last, the robustness of different dynamic CMOS circuits with DVT against the P–V–T fluctuations is discussed in detail.