Noise in strained Si MOSFETs for low-power applications

Abstract

A theoretical study of the thermal noise in strained n-channel Si/SiGe MOSFETs(metal–oxide–semiconductor field effect transistors) is presented. The study was carried outusing a 2D device simulator based on the hydrodynamic model and the impedance fieldmethod, to self-consistently obtain the current noise at the device’s terminals. The analysisfocused on the possible benefits of the scaling on the AC and noise performance of thetransistor for low-power applications. A pure scaling of the transistor’s gate lengthis detrimental to subthreshold operation in terms of the minimum noise figure(NFmin), but would leadto lower values of NFmin for medium and high current levels. Scaling the oxide thickness would not affectNFmin in subthreshold operation, but it will be detrimental for medium and high current levels. Acombined scaling of the oxide thickness and the gate length mitigates the degradation ofNFmin in subthreshold operation when the device geometry shrinks, at the cost of eliminating theNFmin reduction related to the shortening of the gate length at higher current levels.