Abstract

Due to the request for smaller, faster, and more efficient metal-oxide-semiconductor field-effect transistors (MOSFETs), down-scaling has become a current trend of device development. As the dimensions of device are scaled, random telegraph signals (RTS) play an important role in the development of scaling technologies. Hence, researching the electronic property in the presence of RTS in nano-scale devices is becoming a challenging issue. These signals are generally considered as carrier trapping-detrapping from a defect situated in the silicon oxide. When a carrier is trapped, the trapped carrier will produce an additional screened Coulomb potential in the silicon oxide affecting the carriers in channel, and it makes the drain/source current fluctuate between two discrete levels as a trapping-detrapping process. In the experiment, it is not easy to observe the relation between drain/source current variation and the parameters which may impact RTS phenomenon. The one reason is that we cannot modify the characteristic of real devices as we want, and the other reason is that it is difficult to find RTS events across the whole wafer. However, we can solve these problems by using TCAD simulation. In TCAD simulation, we can control the device characteristics by setting any parameters such as gate length, gate width, and doping concentrate, and insert a trap into silicon oxide to make sure the occurrence of RTS events in structure. Building a new physical model of RTS is the major purpose in this thesis. Before building it, we have to characterize the practical device to get experimental data, and analyze its identity by simulating RTS phenomenon by TCAD. First, we built a MOSFET structure with different device sizes, different trap sizes, and different trap positions. By comparing the variation of drain/source current with different parameters, the trend of drain / source current variation changing with each of parameters can be obtained: (1) The rate of drain current change is larger when device size is smaller; (2) There is a peak in the curve for the rate of drain current change, and when device size is scaled, the peak will become sharper and sharper; (3) When the devices with the same width, the curve slopes for the drain current change rate in the subthreshold region are also the same; (4) Drain/source current of trap at gate center of device is smaller than trap at gate edge; and (5) Drain/source current of trap near the source is smaller than trap near the drain. Second, after getting and analyzing the result, we assumed that in the same gate bias, the rate of drain current change would only relate to gate width ( ) instead of both gate width and gate length ( ) when it is in subthreshold region. Then, we verified the trap size in the TCAD simulation while determining the trap size in the model derivation; and vice versa. Based on the simulated result, we combined the two models into a new one using Boltzmann function so that there are two distinct characteristics, in subthreshold region and in strong inversion region. Then, it is a straight focused task to enable the application of the new model in the reproduction of experimental data.

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