Abstract
The recording of neural signals with small monolithically integrated amplifiers is of high interest in research as well as in commercial applications, where it is common to acquire 100 or more channels in parallel. This paper reviews the recent developments in low-noise biomedical amplifier design based on CMOS technology, including lateral bipolar devices. Seven major circuit topology categories are identified and analyzed on a per-channel basis in terms of their noise-efficiency factor (NEF), input-referred absolute noise, current consumption, and area. A historical trend towards lower NEF is observed whilst absolute noise power and current consumption exhibit a widespread over more than five orders of magnitude. The performance of lateral bipolar transistors as amplifier input devices is examined by transistor-level simulations and measurements from five different prototype designs fabricated in 180 nm and 350 nm CMOS technology. The lowest measured noise floor is 9.9 nV/√Hz with a 10 µA bias current, which results in a NEF of 1.2.
Highlights
Wearable and implantable devices for the recording of neural signals receive increasing interest in medicine and behavioral research
The use of folded-cascode amplifiers is a standard technique in CMOS amplifier design, as high linear range, wide common-mode range, and high bandwidth can be achieved with only a few transistors
We examine different lateral bipolar junction transistors (BJT) implementations for their key performance parameters based on measured prototype devices manufactured in 350 nm and 180 nm CMOS technologies
Summary
Wearable and implantable devices for the recording of neural signals receive increasing interest in medicine and behavioral research. The pre-amplifier has to be designed very carefully to yield low input-referred noise (IRN), and its voltage gain is high. The gain requirement results from the signal amplitude in the micro- to millivolt range that is amplified to the typical voltage range of integrated analog electronic circuits of about 1 V to 5 V, depending on technology. Simplified schematic diagrams of each of the approaches are shown in Figure 1a–f and are briefly described as follows
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