Circuits and Systems for Multi-Channel Neural Recording

Abstract

This chapter presents three different circuits and systems architectures enabling multichannel neural recording. These systems preserve the temporal information of the recording sites by avoiding time -multiplexed operation of the ADC. Moreover, various system-level original concepts are introduced that improve trade-offs between noise, power, and silicon area. Oversampling is introduced in Sect. 5.2 as a useful technique to improve the noise efficiency factor (NEF) at system level. Since the total power consumption is dominated by low-noise front-end amplifiers, any increase in the power consumption of the ADC due to the oversampling, has a negligible impact on the overall power consumption of the system. Nevertheless, the input-referred noise is reduced using an oversampling ADC, as the integrated noise bandwidth is reduced by increasing the oversampling ratio, which results in an improved noise efficiency factor (NEF). A 16-channel neural action potential recording IC is presented as a proof-of-concept prototype. A closed-loop gain of 60 dB in the action potential band is achieved by cascading differential gain -stages utilizing a novel common-mode feedback (CMFB) circuit. An oversampling delta modulator (DM) serves as an ADC in order to improve the NEF of the recording system. Moreover, in-site compression is achieved by converting the temporal difference of the input neural signal. The DM employs a novel dynamic voltage comparator with a partial reset preamplifier, which enhances the mean time to failure of the modulator. The proposed architecture is fabricated in a \(0.18\,\upmu \mathrm{{m}}\) CMOS technology. The 16-channel system consumes \(220\,\upmu \mathrm{{W}}\) from a 1.2 V power supply. The SNDR is measured at 28.3 and 35.9 dB at the modulator and demodulator outputs, respectively. The total integrated in-band input-referred noise is measured at \(2.8\,\upmu \mathrm{{V}}_{\mathrm{{rms}}}\), which corresponds to \(\mathrm{{NEF}}=4.6\) for the entire system. Section 5.3 introduces the application of algebraic coding to a multi-channel neural recording system. Walsh-Hadamard coding enables back-end hardware sharing between recording channels employing a single ADC, thereby avoiding time -multiplexing. A single ADC converts the analog superposition of multiple channels. Thus, the dynamic range of the ADC is effectively shared between channels benefiting from the sparsity characteristics of the channels in space domain . Also, noise coupling, interference, and crosstalk are reduced, thanks to the low-impedance and low-swing wired summation of the channels in the analog domain . A 16-channel recording system is developed as a test vehicle. This system provides 60 dB of accurate gain for signal amplification and is programmable by steps of 19 dB. A single 10-bit SAR ADC is used for data conversion. The system is implemented in a \(0.18\,\upmu \mathrm{{m}}\) CMOS technology and occupies a silicon area of \(1.99\,\mathrm{{mm}}^{2}\). Placing the ADC outside of the sensor plane enables reducing the channel’s pitch, with respect to the standard value of \(400\,\upmu {\mathrm{{m}}}\) which is used in Utah’s MEA. The input-referred noise of a single channel integrated from 100 Hz to 100 kHz is simulated at \(4.1\,\upmu \mathrm{{V}}_{\mathrm{{rms}}}\) while consuming \(359\,\upmu \mathrm{{W}}\) from a 1.2 V power supply, which results in a system-level NEF of 5.6. Finally, a 64-channel neural recording system-on-a-chip (SoC) is presented in Sect. 5.4. The system is composed of an on-chip half-wave voltage rectifier, low-voltage bandgap reference circuit, LDO voltage regulator, on-chip reference generator, 64-channel mixed-signal core with dedicated 8-bit SAR ADC per channel, and an on-chip digital ASIC for packet generation , scrambling, and synchronization. A programmable power management technique is proposed which enables dynamic power scaling (DPS) of the mixed-signal core. Applying the DPS technique, the power consumption of each individual channel is reduced by 20.4 % which is equivalent to a reduction of 16 % in the total power consumption of the analog/mixed-mode front-end. The total power dissipation of the SoC is measured at 3.26 mW from a 1.2 V power supply. The SoC is fabricated in a \(0.18\,\upmu \mathrm{{m}}\) CMOS technology and occupies an active silicon area of \(17.5\,\mathrm{{mm}}^{2}\).