Abstract
The author introduces a distributed, circuit-partitioning-based algorithm for fault simulation of both combinational and sequential digital designs. In this approach, referred to as NODIFS, every component in the circuit is modeled as an asynchronous, concurrent entity that is fault simulated as soon as appropriate transitions and fault lists are asserted as its input ports. The circuit is partitioned such that components of ever partition are allocated to a unique processor of the parallel processor system. Consequently, a number of components may be concurrently fault simulated on multiple processors in NODIFS, implying significant increase in throughput. The algorithm is detailed and a mathematical proof of correctness is presented. The performance results indicate significant increase in the speedup for a few representative example digital designs. >
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