No-race charge-recycling complementary pass transistor logic

Abstract

A logic family called no-race charge-recycling complementary pass transistor logic (NCRCPL) is proposed. The use of a new regenerator in NCRCPL leads to a complete elimination of the controller in the circuit hence reducing the number of transistors and power consumption. It has an additional benefit of reduced sensitivity to signal skew. The proposed logic family in its modular structure also has a better performance than previous modular structures based on charge recycling. Furthermore, a latch structure called dual-rail isolated latch which can be used for pipelining NCRCPL has been proposed. The new latch had a much better performance compared with previous static latch structures. To enhance the power efficiency of the pipeline configuration an event-detector circuit is proposed that may reduce the power consumption by up to 50% compared with previous pipeline configurations. To assess the performance improvements of the logic structures of this work compared with other charge recycling logic structures, logic gates and ripple carry adders are studied.