CMOS differential logic family with self-timing and charge-recycling for high-speed and low-power VLSI

Abstract

The paper describes a differential CMOS logic family employing self-timing for speed enhancement and charge recycling for power reduction. The logic family is up to 49% faster than other types of dynamic circuits. A pseudo one-phase clocking pipeline configuration implemented with the proposed logic family can boost clock frequency by eliminating latching stages between pipeline sections. A 64-bit adder designed using the proposed logic family achieves 0.97 ns latency with power dissipation comparable to that of the conventional precharged differential logic family.