Data-dependent evaluating latched CMOS differential logic family for statistical power reduction

Abstract

In this paper, a novel CMOS differential logic family, called data-dependent evaluating latched CMOS logic (DELL), is proposed for use in low-power VLSI. The proposed logic family discharges internal precharge nodes on demand, and thus, statistically reduces the power consumption during logic operation. The self-resetting version of the logic family can also boost the operating clock frequency by performing precharge operation as early as possible. It has the additional advantage of clock power reduction by reducing the clock load. The proposed logic family was designed using 0.35 /spl mu/m CMOS process technology. The comparison results show that the proposed logic family consumes less power than the conventional logic family for the switching activity smaller than 0.7, and achieves a power saving of up to 75%. The improvement of power, delay product is also about 34%.