Abstract
A nitrogen plasma annealing process for gate dielectric applications in 4H-SiC metal oxide semiconductor (MOS) technology has been investigated. This process results in substantially greater interfacial N coverage at the SiO2/4H-SiC interface and lower interface trap densities than the state-of-the-art nitric oxide (NO) annealing process. Despite these exciting results, the field-effect mobility of MOS field-effect transistors (MOSFETs) fabricated by use of this process is very similar to that of NO-annealed MOSFETs. These results emphasize the importance of understanding mobility-limiting mechanisms in addition to charge trapping in next-generation 4H-SiC MOSFETs.
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