Abstract
HCI degradation of pass-gate transistor with forward and reverse stress biases in advanced FinFET technology is investigated comprehensively. Due to the bidirectional stress, pass-gate HCI shows larger degradation than conventional HCI, which can induce up to 50% error in predicting pass-gate delay degradation. Based on the proposed underlying physics, compact model of pass-gate HCI is developed and verified. With further analysis on circuit level, new simulation methodology is demonstrated. It is thus helpful to the reliability-aware circuit design in advanced FinFET technology.
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