Aging Impacts on SOC Timing in Advanced FinFET Technologies

Abstract

SOC (System on Chip) timing closure meets challenges in advanced FinFet technologies with lower voltage and higher frequency. As a part of variation, aging is taking more attention. But capturing the effect of BTI (includes NBTI and PBTI) on timing has been a tedious task and few research shows the detailed aging impact on timing slack and path delay. In the paper, a SOC chip level aging timing analysis methodology is introduced, which has very fast runtime and involved the realistic SP (Signal Probability) in aging degradation. A commercial sub-16nm, ~0.3Billion gate count network chip is used to study the aging impacts on timing with the methodology. With the result, the whole trend of the slack and the path delay changes caused by aging is presented, which could guide designer to a better design.