New dynamic ternary minimum and maximum circuits with reduced switching activity and without any additional voltage sources

Abstract

Ternary minimum AND and maximum OR functions are implemented in this paper based on dynamic logic style, where the clock signal evaluates combinational circuits periodically. Unlike previously presented designs, additional voltage sources are not required in the proposed structures. Transistors divide voltage to achieve standard ternary functions. An initial design is modified gradually to reach a high-performance design with reduced transistor-count and decreased switching activity. New circuits are simulated with carbon nanotube field effect transistor technology in different situations. Simulation results show that the proposed cells are suitable for low-power and high-frequency applications.