Quotient prediction for low power division

Abstract

This work presents a variation of the non restoring division algorithm that has been optimized for low power consumption. The approach uses the value of the partial remainder at any stage in the computation to predict the quotient bits for a certain number of steps thereby allowing an equal number of computation steps to be skipped. This results in a significant reduction in switching activity in the computational stages. Simulations using the novel divider show up to 40% reduction in sequential switching activity and 20% reduction in combinational switching activity. On an average, this method uses 59% less addition operations as compared to the regular non restoring division algorithm.