CNTFET — Based power efficient design of a digital event count comparator

Abstract

This paper presents a novel design which compares a stream of digital data with a threshold value and accumulates the number of occurrences for when the data is above, equal to or below the threshold. The design is implemented using two transistor technologies viz. carbon nanotube (CNT) FETs (CNTFETs) and 32nm CMOS technology in order to shed light on the advantages of using CNTFETs over bulk-silicon transistors. A comparison is drawn on the power consumption and delay involved in the design for both technologies. The CNTFET model being used is obtained from the Verilog-A formulation of the Stanford compact model for CNTFET. Extensive simulation results using Cadence Virtuoso show that the proposed design consumes significantly lower power and has lower delay times when implemented using CNTFETs.