Abstract
In this paper we present a simulation study of a novel Double-Gate (DG) Ferroelectric FET (Fe-FET) architecture, exhibiting a subthreshold swing well below 60 mV/dec with a hysteresis-free behavior. The new device topology is based on the interposition of a floating gate between the ferroelectric layer and the gate oxide. The floating gate can be extended above the source and drain regions, so that its capacitance can be suitably optimized to ensure device stability. We found that both the overlap capacitance and quantum confinement are beneficial for the amplification factor. The ION improvement over the standard DG MOSFET turns out to be 23.7×, with no degradation of the intrinsic transit time.
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