Abstract
In this paper we present a simulation study of a novel Double-Gate (DG) Ferroelectric FET (Fe-FET) architecture, exhibiting a subthreshold swing well below 60 m V /dee with a hysteresis- free behavior. The new device topology is based on the interposition of a floating gate between the ferroelectric layer and the gate oxide. The ferroelectric layer can be extended above the source and drain regions, so that its capacitance can be suitably optimized to ensure device stability. Under the assumption of a fixed mobility, the on-state current improvement over a standard DG MOSFET turns out to be 86%, with a degradation of the intrinsic delay time of about 12%.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
