Multigate and Nanowire Transistors

Abstract

As presented in Chapter 1, the use of a multigate architecture is a technology booster that allows improved electrostatic control of a channel region by the gate electrode, and therefore mitigates short-channel effects. Currently existing multigate architectures for the MOSFET are described, and then compared in terms of short-channel effect control. It is concluded that the gate-all-around structure associated with a nanowire-shaped semiconductor offers the best possible electrostatic control of a channel. Different effects arising from carrier confinement effects in semiconductor nanowires are considered. The chapter concludes with a discussion of novel phenomena arising from quantum confinement, such as the semimetal–semiconductor transition, band folding of the electronic structure in nanowires, and novel devices that can be devised on the nanometer length scale. Introduction In the classical planar MOSFET, the gate dielectric and gate electrode sit above the channel region. Electrostatic control of the channel by the gate is achieved through the capacitive coupling between the gate and the channel. To maintain transistor scaling laws, a reduction in the depths of the source and drain regions by the same factor as the gate length reduction is required. This reduces short-channel effects at the cost of rendering less effective the control of the channel region through source and drain voltages. High- κ dielectrics are used as gate oxide materials to increase current drive without having to pay a stiff penalty in gate oxide leakage, which is in turn largely responsible for standby power consumption. Decreasing the equivalent gate oxide thickness (EOT) through the replacement of the silicon dioxide insulating layer by metallic oxides with higher dielectric constant improves the capacitive coupling between the gate and the channel, and thus also reduces short-channel effects. The electrostatics of a planar, long-channel MOSFET can be reduced in a first approximation to a one-dimensional problem. Early textbooks on semiconductor device physics introduced the “gradual channel approximation,” which can be solved by Poisson's equation – the equation that governs the relationship between electric fields and electrical charges – in one dimension, vertically from the gate through the channel and down through the silicon substrate. Short-channel effects whereby electric fields from the source and the drain encroach laterally (horizontally) in the channel region introduce a second dimension to the problem. In planar MOSFETs on bulk silicon, short-channel effects become insurmountable once the gate length becomes smaller than approximately 15 to 20 nm.