New design flows for high density programmable logic designers

Abstract

Now that programmable logic devices with gate densities of over 100 K gates are commonly available, field programmable gate array (FPGA) and complex programmable logic device (CPLD) designers are adopting new design flows to take advantage of their power. These design flows are based on a high level design methodology with advanced logic synthesis technology. In addition, they require other sophisticated design tools that, in the recent past, were exclusively part of the ASIC design realm. This paper discusses the new challenges that programmable logic designers face and the recent developments in design tools and design flows to satisfy their requirements.