Abstract
In this paper, we propose a new modeling method for computing coupling capacitance between interconnects on the same or different layers and substrate capacitance in the nanometer very large-scale integration circuits. The model has been developed based on a template, which is obtained on the basis of electric field approximation and followed by a curve-fitting technique to reach promising accuracy. To verify our proposed model, we develop scripts to generate thousands of layout samples which cover all possible geometric situations for CMOS 180-, 90-, and 65-nm technologies. The proposed model is compared with previously published works with reference to the extracted results from commercial tools. The experimental results show that the estimation errors of our method are much lower than 10% (2%–4% or less for most of the cases) but with significantly reduced computation effort. The proposed model is a general methodology that can be used for any nanometer technologies with different geometric parameters.
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