Abstract
The key feature of NCFET (negative capacitance field effect transistor) is its sub-threshold slope (SS) < 60 mV/decade at 300 K. In this work, the n-type NCFET (i.e., pull-down (PD) and passgate (PG) transistor in six-transistor (6T) SRAM bit-cell) has SS of 53.92 mV/decade, and the p-type NCFET (i.e., pull-up (PU) transistor in the 6T SRAM bit-cell) has SS of 58.96 mV/decade. In the NCFET-based SRAM cell (vs. conventional SRAM cell with conventional planar bulk MOSFETs), its read (hold)-stability and write-ability are evaluated by the metric of read static noise margin (SNM) and write-ability current (Iw), respectively. Then, under process-induced random variation, sensitivities of SNM and Iw are extracted. Finally, the yield of NCFET-based SRAM array (vs. conventional SRAM array) is quantitatively estimated using the cell-sigma.
Highlights
The cache memory in digital computer has been playing a key role of processing/fetching data in-between central processing unit (CPU) and main memory (DRAM)
The yield estimation is based on the cell sigma concept, and the variables for estimating the cell sigma are W, L, and VTlin
When 20nm-long short channel devices are used in SRAM bit-cell, the channel length variation has been found to have the greatest effect on SRAM yield
Summary
The cache memory (static random access memory, or SRAM) in digital computer has been playing a key role of processing/fetching data in-between central processing unit (CPU) and main memory (DRAM). VARIATION-AWARE SENSITIVITY ANALYSIS Due to various deviations in the process of manufacturing IC chips, device parameters of six transistors that make up a 6-T SRAM bit-cell is not completely fabricated as originally designed. The sensitivity of SNM and Iw to each of six transistors (i.e., PD1, PD2, PG3, PG4, PU5, and PU6) are measured by three variation parameters (i.e., channel width, channel length, and VTlin).
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