Abstract
We report a broad study of Negative Bias Temperature Instability (NBTI) in Replacement Metal Gate (RMG) SiGe core FinFETs, focusing on the impact of Ge concentration, fin width, fin side-wall orientation, and interface passivation by high pressure anneals (HPA). We focus on Si-cap-free gate stacks, which offer simplified FinFET integration. Direct oxidation of SiGe yields poor interface quality, which can be restored by HPA. Despite a wide distribution of defect levels in the interfacial layer due to Ge suboxide formation, SiGe reliability still benefits from a reduced bulk oxide trapping thanks to favorable energy decoupling of channel carriers to dielectric defect levels. Reduced NBTI is observed in narrow fins, thanks to a reduced oxide electric field. Fin rotation does not improve NBTI in SiGe fins, while some improvement, particularly of the near-interface degradation, was obtained by HPA. Our results show that Si-cap-free RMG SiGe gate stacks with properly optimized HPA can offer a simplified FinFET integration, with a limited reliability penalty compared to best-in-class Si-passivated SiGe devices.
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