Nanoscale Two-Bit/Cell NAND Silicon–Oxide–Nitride–Oxide–Silicon Devices Designed on Fully Depleted Silicon-on-Insulator Substrates

Abstract

Nanoscale 2-bit/cell NAND silicon–oxide–nitride–oxide–silicon (SONOS) memory devices with two separated control gates utilizing a fully depleted silicon-on-insulator (SOI) structure were designed. The program and erase characteristics of the proposed unique nanoscale 2-bit/cell NAND SONOS memory devices were simulated using technology computer-aided design tools. Simulation results showed that the leakage current in the subthreshold region and the subthreshold swing for the nanoscale 2-bit/cell NAND SONOS memory devices were decreased by utilizing a SOI structure. The initial threshold voltage of the nanoscale 2-bit/cell NAND SONOS memory devices with a SOI structure was larger than that of conventional SONOS devices without a SOI structure, indicative of a decrease in leakage current. Simulation results showed that the short-channel effects in the nanoscale 2-bit/cell NAND SONOS memory devices decreased in magnitude owing to a larger effective channel length.