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Abstract
Split-gate engineering has been studied to improve metal-oxide-semiconductor-field-effect-transistors (MOSFETs) down to the 45 nm regime, and it is shown that a properly designed split-gate device can improve both frequency performance and intrinsic gain for a wide range of channel lengths due to enhanced carrier transport and reduced short-channel effects. The relative gate length percentage in the split-gate device can optimize device performance based on cut-off frequency, intrinsic gain and threshold voltage considerations. Its output resistance behavior following drain-induced barrier lowering (DIBL) is studied; sidewall spacer width and substrate doping effect on device RF/analog performance are also discussed in this context.
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