Abstract
In the last decade, the rapid emergence and popularity of reusable core-based designs, poses new challenges to the test-dedicated circuitry, specifically IEEE 1149.1 test access port (TAP) standard. The modern cores tend to have a build-in TAP to facilitate both on-chip design for test (DFT) and design for debug (DFD) implementation and reuse. That has triggered development of numerous multi-TAP architectures. Selecting the correct architecture is considered a key point in reduction of testing and debugging efforts, decreasing test time, as well as allowing effortless architectural reuse across different platforms and integrated circuits (ICs). This paper makes an attempt to fill the gap in presenting a thorough analysis of existing multi-tap architectures yielding the resulting classification, comparison and summary of all the major multi-TAP architectures. Several modifications to the existing architectures are proposed and analyzed in detail.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
