Multi-Resolution Block Matching Algorithm and Its VLSI Architecture for Fast Motion Estimation in an MPEG-2 Video Encoder

Abstract

This paper proposes a high-performance multi-resolution motion estimation algorithm (HMRME) for MPEG-2 video encoding, which satisfies high estimation performance and efficient very large scale integration (VLSI) implementation. HMRME is based on a characteristic that field motion vectors (MVs) are very similar to their corresponding frame MV. Firstly, HMRME performs frame-based motion estimation (ME) as follows: at the coarsest level, two MV candidates are found on the basis of minimum matching error. The two MV candidates from the coarsest level search and the other one based on spatial MV correlation are used as center points for three local searches at the middle level. At the finest level, a frame MV is obtained from a local search around a single candidate from the middle level search. Field MVs are estimated with the single MV candidate from the middle level search of frame ME as initial estimates at the finest level, without any coarser level searches. This paper also describes a VLSI architecture based on HMRME. This architecture is designed to provide a good tradeoff between on-chip memory size and I/O bandwidth with high throughput. We implemented this architecture with about 140 K gates and 2.5 K bytes static random access memory for a large search range of [-192.0, +191.5] by using a synthesizable Verilog HDL.