Multiresolution block matching algorithm and its LSI architecture for fast motion estimation in MPEG-2 video encoder

Abstract

This paper proposes a fast multi-resolution block-matching algorithm (MRBMA) for MPEG-2 video encoding, which satisfies high estimation performance and efficient LSI implementation. MRBMA is based on the characteristic that field motion vector’s (MV’s) are very close to its corresponding frame MV. Firstly, MRBMA performs frame-based motion estimation (ME) as follows: At the coarsest level, two MV candidates are found on the basis of minimum matching error for the next level search. The two MV candidates from the coarsest level search and the other one based on spatial MV correlation are used as center points for three local searches at the middle level. At the finest level, a frame MV is obtained from a local search around a single candidate from the middle level search. Field MV’s are estimated with the single MV candidate from the middle level search of frame ME as initial estimates at the finest level, without any coarser level searches. This paper also describes a VLSI architecture based on MRBMA. This architecture is optimized to provide a good tradeoff between on-chip memory size and I/O bandwidth with high throughput. We implemented this architecture with about 140K gates and 25K bytes SRAM for a large search range of [-192.0, +191.5] by using a synthesizable Verilog HDL.