Multiple thickness gate oxides with fluorine implantation for system on chip applications

Abstract

Integrating digital, analog, I/O and memories onto a single chip is a great challenge to the design and process engineers. From the process engineers' point of view, integrating these modules with conflicting requirements needs a lot of innovation in the process technology. One such requirement is the need of having multiple gate oxide thickness on the same chip. Fluorine implantation of variable doses is explored to achieve this goal. It has been found that by varying the implanted dose of the fluorine in silicon, the oxidation rate and thereby the oxide thickness can be varied. The electrical characterization of the fluorine-implanted silicon based MOS structures using C– V and J– E measurements is reported here. It has been found that one can control the oxide thickness, interface properties and threshold voltage that could be vital in the SOC level integration.