Multiple Bit Error Correction Codes for Memories in Satellites

Abstract

This paper proposes a new Error Correction Code (ECC) for 32-bit memory data named Vertical Parity and Diagonal Hamming (VPDH) Code. It is a linear block code which employs 28 parity bits for a 32-bit data and is represented as (60, 32) code. In this work, the proposed VPDH ECC is compared with Burst Error Correction codes (BEC) and Horizontal-Vertical Parity and Diagonal Hamming (HVPDH) ECC in terms of number of errors corrected, power, delay, area, code rate and bit overhead. VPDH ECC corrects about 30% more 3-bit errors, 24% more 4-bit errors and around 6% more 5-bit errors than HVPDH ECC with the same code rate, power and bit overhead but with a small increase in delay. With the same area and number of parity bits, VPDH ECC offers enhanced error correction capabilities when compared to HVPDH ECC. The VPDH Encoder and Decoder are simulated and synthesized in Xilinx Vivado using a 180nm standard cell library. The design is validated by intelligent test bench automation. Due to its enhanced error correction capabilities, this ECC is therefore ideal for satellite and outer space applications where the on board computers face the issue of soft errors by external cosmic radiations.