Error Control Codes Based Modified Orthogonal Latin Squares for High-Speed Cache Memories

Abstract

Traditionally, error control codes (ECCs) have been employed to protect cache memory from hard and soft errors. Single error correction (SEC) codes are commonly used in high-speed caches due to their simple and fast decoding circuitry. As the technology feature size shrinks, the incidence of errors in cache bit cells increases. To improve cache reliability, single error correction double error detection (SECDED) codes are used. Conventional SECDED codes focus on reducing the number of parity bits that are stored with each data word within the cache, thereby minimizing the overhead associated with cache storage. However, in high-speed cache memory, the less-delay decoder circuit is a key factor for adopting SECDED codes. Orthogonal Latin square (OLS) codes are a type of one-step majority-logic-decodable (OS-MLD) codes that offer the fastest decoding process. However, they require more parity bits than conventional SECDED codes, which limits their usefulness in area-sensitive high-speed cache applications. Therefore, the development of a new SECDED based on OLS codes with a balance between the number of parity bits and decoding speed can be an attractive solution for high performance cache designers. Recently, a modified SEC OLS code has been proposed, which significantly reduces the required number of stored parity bits, while maintaining the simplicity and speed of the decoding circuit. In this paper, a class of SECDED codes based on the modified SEC OLS codes will be presented. The codes perform both error correction and detection in parallel with a low number of parity bits compared to the original SEC OLS codes. The reduction in parity bits reaches 18.7% and 21.8% when the proposed SECDED codes are implemented to protect 64-bit and 256-bit data words, respectively. Based on the FPGA and ASIC synthesis results, it is evident that the proposed SECDED codes provide a promising solution for protecting high-speed cache memory applications. These codes exhibit a significant reduction in decoding delay time when compared to existing SECDED codes. In fact, the proposed codes are capable of effectively protecting cache applications with 0.5 ns clock targets.