Multi-clock domain TDF ATPG testing: An innovative approach

Abstract

With the rapid advancement of fab process technology into the nanometer node era, there is an increasing trend in the manifestation of deep submicron (DSM) marginal defects in integrated circuit (IC) fabrication. Despite transition delay fault (TDF) tests providing reasonable coverage against DSM marginal defects, this methodology is hampered in designs with multiple clock domains where the lowest operating clock frequency becomes the dominant TDF testing frequency. The methodology advocated in this paper aims to overcome this bottleneck by introducing an automated yet comprehensive approach to segregate and consolidate the various clock domains in any design for more effective TDF testing. It identifies all user registers in the design and recursively identifies the clock sources of those registers through intelligent net connectivity analysis. In an experimental 200M-transistor and 4-clock-domains test-chip netlist, this methodology is able to identify clock sources for all registers in five minutes time, and that processing time is negligible when compared to the TDF automatic test pattern generation (ATPG) time. Hence, it has been proven effective and highly successful in increasing the TDF test frequency to the highest operating clock domain frequency of the design.