Case Studies on Transition Fault Test Generation for At-speed Scan Testing

Abstract

At-speed scan testing for intra-clock and inter-clock transition delay faults in a SOC design with multiple clock domains is an important and challenging issue. Current practice in industry usually applies a test scheme targeted on intra-clock transition fault delay testing (i.e., intra testing). In this paper a test scheme targeting both intra-clock and inter-clock domains for transition delay fault testing (i.e., intra-inter testing) is applied. This paper presents an empirical study by comparing between intra testing and intra-inter testing in terms of fault classification, test detection, test coverage, test volume, and test power by using industrial circuits. The information provided by this paper is beneficial to both practitioners and researchers in their pursuit of improving the quality of transition delay testing, which is critical to the quality of deep-sub micron VLSI chips.