Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model

Abstract

For high-performance integrated circuits with tight timing budgets, full-scan based transition delay fault (TDF) testing is mandatory to ensure high test quality. However, the discrepancy between the scan test mode and the functional mode is problematic. For example, the elevated switching activity during scan test application may degrade circuit performance and lead to overkill. In this paper, we address this problem by generating functional-like TDF test patterns. First, a Bayesian-based circuit model is constructed; the result is an enumeration of circuit states that closely mimics the functional mode. During test generation, the model guides the backtrace and fault propagation procedures more effectively than the conventional SCOAP or COP measures because reconvergent fanout is implicitly included in the model. Experimental results on processor benchmarks, including a MIPS32 and a RISC-V processor, show that the TDF test set generated using the Bayesian-based circuit model not only is more functional-like, but also achieves higher fault coverage.