Abstract

In this paper, we present a digital spike detector using an adaptive threshold which is suitable for real time processing of 32 electrophysiological channels in parallel. Such a new scheme is based on a Sigma-delta control loop that precisely estimates the standard deviation of the amplitude of the noise of the input signal to optimize the detection rate. Additionally, it is not dependent on the amplitude of the input signal thanks to a robust algorithm. The spike detector is implemented inside a Spartan-6 FPGA using low resources, only FPGA basic logic blocks, and is using a low clock frequency under 6 MHz for minimal power consumption. We present a comparison showing that the proposed system can compete with a dedicated off-line spike detection software. The whole system achieves up to 100% of true positive detection rate for SNRs down to 5 dB while achieving 62.3% of true positive detection rate for an SNR as low as -2 dB at a 150 AP/s firing rate.

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