Multi-level factorisation technique for pass transistor logic

Abstract

There is discussion of a technique of using multi-level logic synthesis to design pass transistor logic (PTL) based on algebraic factorisation. Techniques already applied to conventional AND-OR type networks are shown to be not useful for factorisation of PTL networks. Starting with the set of all prime pass implicants, the steps of selecting a cover and factorising a function, using a greedy heuristic, are combined. From many examples using MCNC benchmark circuits, the algorithm achieves a considerable improvement (an average of 14% and up to 50% savings) over PTL circuits obtained from conventional two-level design methods.