Abstract
Pass transistor logic (PTL) circuits are known to be well suited for pipelined circuits and have been receiving considerable interest in recent times. Existing techniques for synthesizing PTL circuits are based on two level networks of transistors. In this paper, we have proposed a new decision diagram based model for multilevel PTL circuits. We have described a number of transformations on our model. Using these transformations, we have developed a top down greedy heuristic for synthesizing PTL circuits and have established that our synthesis techniques give us significant savings compared to existing synthesis procedures.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
