A method for synthesizing area efficient multilevel PTL circuits

Abstract

Pass transistor logic (PTL) circuits are known to be well suited for pipelined circuits and have been receiving considerable interest in recent times. Existing techniques for synthesizing PTL circuits are based on two level networks of transistors. In this paper, we have proposed a new decision diagram based model for multilevel PTL circuits. We have described a number of transformations on our model. Using these transformations, we have developed a top down greedy heuristic for synthesizing PTL circuits and have established that our synthesis techniques give us significant savings compared to existing synthesis procedures.