Multi‐FPGA Partitioning Method Based on Topological Levelization

Nabil Kerkiz,Amr Elchouemi,Don Bouldin

doi:10.1155/2010/709487

Nabil Kerkiz, Amr Elchouemi + Show 1 more

Open Access

https://doi.org/10.1155/2010/709487

Copy DOI

Abstract

This paper presents a partitioning method based on topological ordering and levelization. The proposed method, termed RPL, performs multi‐FPGA partitioning by taking into account six different partitioning constraints. We also compare RPL to two existing algorithms. The first approach is a hierarchical partitioning method based on topological ordering (HP). The second approach is a recursive algorithm based on the Fiduccia and Mattheyses bipartitioning heuristic (RP). Experimental results on seven application benchmarks mapped onto three different hardware architectures demonstrated that the proposed RPL approach achieved fewer partitions in less time when compared to the RP and HP algorithms.

Highlights

An adaptive computing system (ACS) composed of programmable logic components can serve as a flexible hardware accelerator for applications in domains such as image processing and digital signal processing
The first approach is a hierarchical partitioning method based on topological ordering (HP)
The second approach is a recursive algorithm based on the Fiduccia and Mattheyses bipartitioning heuristic (RP)

Summary

Introduction

An adaptive computing system (ACS) composed of programmable logic components can serve as a flexible hardware accelerator for applications in domains such as image processing and digital signal processing. To enable application designers to automatically map their applications onto ACSs, a software design environment called CHAMPION was developed at the University of Tennessee. This environment permits high-level design entry using the Cantata graphical programming software [1, 2]. The graph-based subnetlists are translated into structural VHDL files. Place and route software tools are used to map the synthesized netlists to the programmable logic components and to obtain the programming bit files. The final step in the design flow is to automatically generate the host program which initializes the ACS board and downloads the programming bit files for each programmable logic component

Hardware Architectures

Problem Formulation

Partitioning Approaches

Experimental Results and Discussion

Conclusion