Monitoring Wafer Map Data From Integrated Circuit Fabrication Processes for Spatially Clustered Defects

Abstract

Quality control in integrated circuit (IC) fabrication has traditionally been based on overall summary data such as lot or wafer yield. These measures are adequate if the defective IC's are distributed randomly both within and across wafers in a lot. In practice, however, the defects often occur in clusters or display other systematic patterns, In general, these spatially clustered defects have assignable causes that can be traced to individual machines or to a series of process steps that did not meet specified requirements. In this article, we develop methods for routinely monitoring probe test data at the wafer map level to detect the presence of spatial clustering. The statistical properties of a family of monitoring statistics are developed under various null and alternative situations of interest, and the resulting methodology is applied to manufacturing data.