Use of wafer maps in integrated circuit manufacturing

Abstract

A wafer map identifies the locations of defective integrated circuits (chips) on a silicon wafer and provides important spatial information. The wafer yield is a useful measure of the process quality, but other features are necessary to account for. Careful statistical analysis addressing the spatial information in the wafer map is necessary in order to monitor the quality of the manufacturing process, and identify/eliminate fault sources with assignable causes. We discuss simple descriptive analyses of wafer map data, as well as formal statistical methods, based on three different models that account for different spatial patterns. In particular, the models support the observed phenomenon that the faults are distributed non-uniformly across the wafer, by allowing the fault probability to vary across the wafer, and allowing faults at adjacent locations to be statistically dependent.