Monitoring of stress reduction in shallow trench isolation CMOS structures via synchrotron X-ray topography, electrical data and raman spectroscopy

Abstract

Local oxidation of silicon (LOCOS) isolation technology is becoming increasingly unusable for critical dimensions of 0.25 μm and below, due to the intolerably large dimension of the oxide “bird'sbeak”. Therefore, this technique has been replaced by a process called shallow trench isolation (STI) which uses deposited dielectrics to fill trenches etched in the silicon between the active areas. One of the chief drawbacks to STI is the tendency of such structures to be highly stressed, especially after the oxide/dielectric backfill, which can have a deleterious impact on the electrical performance of fabricated devices. It is essential to monitor the stress/strain fields generated by shallow trench isolation structures. Synchrotron X-ray topography (SXRT), a genuinely non-destructive technique, has been employed to provide in situ stress evaluation during the development of an STI-based complimentary metal oxide semiconductor (CMOS) integrated circuit process. Various process options were evaluated and the data was compared with electrical n+/p diode leakage and micro-Raman spectroscopy data.