Abstract
The design of programming/erasing (P/E) coupling ratios of advanced low-power embedded flash cells (working as an on/off switch) with a shallow trench isolation (STI) structure has been discussed to meet future performance requirement. The reason that the stress-induced reliability degradation (SIRD) problem becomes more severe when the STI structure is used in a low-power flash cell has also been clearly explained. In this paper, we suggest a drain (or source) side erase method for both lower-voltage operation and quick data writing. This device must be operated at a suitable bias condition to achieve the best reliability. For further improvement in the control and uniformity of the reliability performance, a modified STI module and modified cell drain side engineering are proposed and verified on a 256 K NOR-type embedded low-power flash test vehicle.
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