Abstract
A set of soft IP cores for the Winogradr-point fast Fourier transform (FFT) is considered. The cores are designed by the method of spatial SDF mapping into the hardware, which provides the minimized hardware volume at the cost of slowdown of the algorithm byrtimes. Their clock frequency is equal to the data sampling frequency. The cores are intended for the high-speed pipelined FFT processors, which are implemented in FPGA.
Highlights
Fast Fourier transform (FFT) algorithm is widely used in many signal processing and communication systems
In this paper we propose the design of a set of r-point discrete Fourier transform (DFT) units, which help to implement the pipelined FFT processors, when the data flow is a single sample per a clock cycle
The implementation of the r-point DFT modules in field programmable gate arrays (FPGAs) provides the design of the high-speed pipelined FFT processors with optimized hardware volume
Summary
Fast Fourier transform (FFT) algorithm is widely used in many signal processing and communication systems. Due to its intensive computational requirements, it occupies large area and consumes high power if implemented in hardware. FFT uses divide and conquer approach to reduce the computations of the discrete Fourier transform (DFT). In Cooley-Tukey radix-2 algorithm, the N-point DFT is subdivided into two (N/2)-point DFTs and (N/2)-point DFT is recursively divided into smaller DFTs until a two-point DFT. The last procedure, named as radix-2 butterfly, is just an addition and a subtraction of complex numbers. Higher radix algorithms, such as radix-4 and radix-8, can be employed to reduce the complex multiplications, but the butterfly structure becomes complex. A split radix algorithm [1] is adopted to get the benefits of both radix-2 and radix-4 algorithms
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