Abstract
An analytical model of the I– V input curves of normally on JFET structures for an arbitrary drain voltage is proposed. The model is capable to predict the occurrence of a negative resistance in the curves in agreement with numerical simulations and experiments. It is shown that, similarly to the unijunction transistor, the negative resistance is determined by the variation of the ohmic drain voltage occurring in the base as the gate voltage reaches the onset value of the conductivity modulation regime. Moreover the model can be considered the basic theory of the experimental method proposed [Solid-State Electron 43(7) (1999) 1201] for measuring the series resistance of lateral diodes.
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