Modeling Size Limitations of Resistive Crossbar Array With Cell Selectors

Abstract

Due to recent developments in emerging memory technologies, resistive crossbar arrays have gained increasing importance. The size of the crossbar arrays is, however, limited due to challenges brought by the interconnect resistance, sneak path currents, and the physical area of the peripheral circuitry. In this paper, three figures of merit that characterize the limitations of resistive crossbar arrays with selectors are described, such as the driver resistance, voltage degradation across the cell, and read margin. The models, exhibiting good agreement with SPICE, are compared with different biasing schemes during both write and read operations. These models are also used to predict the device requirements of resistive crossbar arrays with selectors and to project parameter values, such as the nonlinearity factor, on-state resistance, and tolerable interconnect resistance per cell for large-scale crossbar arrays.