Design models of resistive crossbar arrays with selector devices

Abstract

Due to recent developments in emerging memory technologies such as MRAM/RRAM, resistive crossbar arrays have gained increasing importance. The size of the crossbar arrays is, however, limited due to challenges brought by the interconnect resistance, sneak path currents, and the physical area of the peripheral circuitry. In this paper, three figures of merit that characterize the limitations of resistive crossbar arrays with select ors, the driver resistance, voltage degradation across the cell, and read margin, are discussed. Models are described that exhibit good agreement with SPICE, exhibiting a maximum error of 6.5% for the worst case voltage degradation during a write operation and 6% during a read operation for voltage ratios above, respectively, 0.5 and 0.25. Furthermore, these models are used to predict device requirements of resistive crossbar arrays with selectors and to project parameter values such as the nonlinearity factor, resistance in the on state, and tolerable interconnect resistance per cell for large scale crossbar arrays.