Modeling of single-wall carbon nanotube interconnects for different process, temperature, and voltage conditions and investigating timing delay

Abstract

The performance of Single-Wall Carbon Nanotube (SWCNT) based interconnect is investigated in this paper. CNT has become the most promising replacement for Cu based interconnects in future VLSI technologies in the nanometer regime. The process, temperature, and voltage (PTV) dependent equivalent circuit model for CNT based interconnect is developed. The performances of Cu and CNT based interconnects are compared for different ITRS technology nodes. The timing delay is analyzed in CNT based interconnect under different PTV conditions for 32 nm and 16 nm technology nodes. Process variation is modeled by considering the variations in CNT diameter, spacing, and metallic fraction. The delay variation is more than 100 % with process variation whereas with voltage and temperature the delay variations are ±20 % and ±50---60 % from the nominal voltage and room temperature, respectively. The diameter variation of CNT has almost no effect on the timing of SWCNT bundle based interconnects.