Timing analysis taking into account interconnect process variation

Abstract

Timing margin becomes smaller and smaller as frequencies increase. Pico-second variations can no longer be ignored, in particular, for high speed clock design. Characterizing and managing process variations of interconnect geometry is becoming critical for .13 micron and below. Process variations not only affect yield, but also have impact on performance and reliability. Delay analysis can no longer ignore process variations for .13 micron and below technologies. It's meaningless for an RC extraction tool to claim within 10% accuracy, without taking into account process variations, which could be over 10% of the nominal value. RC extraction with process variations can never be the final goal. Capacitance variation and resistance variation are meaningless unless they are being converted into delay variation and timing variation. Process variations are not completely random. It can be divided into deterministic part and nondeterministic part. The deterministic part comes from deterministic factors, such as layout patterns, while the nondeterministic part comes from uncertainties in fabrication. Worst cases are not necessarily activated by the extremes of process parameters, performance does not change monotonously or linearly according to process parameters. The worst cases of different nets are activated by different process parameters. There is no corner cases known for process variations on interconnect. A new approach to convert process variation into delay variation and timing variation is presented.