Abstract

The coupling effects among interconnects need to be considered in single event hardening modeling and analysis of combinational logic due to scaling effects that increase both SE susceptibility and coupling effects. SETs generated on an affecting wire due to particle hits on driver transistors can also create delay changes on neighboring victim wires via cross-coupling effects if these lines are in switching. The delay change at victim receiver inputs can later translate into timing violations on the storage elements that are connected to these receivers. This chapter first introduces a worst-case delay (WCD) estimation method for use in design automation tools. Following the model introduction, it presents SE speedup effects caused by crosstalk and then introduces a best-case delay (BCD) estimation methodology. The SE coupling delay and speedup expressions derived show very good results in comparison to HSPICE results while allowing for a faster analysis.

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