Abstract
Due to scaling effects, integrated circuits are becoming more sensitive to transient pulses and delay effects caused by single event (SE) particles. In addition, cross-coupling effects among wires can cause SE transients to spread other paths of the circuit which may increase the SE vulnerability of CMOS circuits. The coupling effects among interconnects need to be considered in single event modeling and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. This work studies the effect of SE coupling on circuit delays and proposes a worst-case delay estimation method for use in design automation tools for the first time to our knowledge. The SE coupling delay expressions derived show very good results in comparison to HSPICE results. Results show an average error of about 6.3 % for worst-case delay while allowing for very fast analysis in comparison to HSPICE.
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