Modeling of Double-Gate Field-Effect Diodes for Analog Applications

Abstract

As technological trends impose device dimension limitations, exploring other devices apart from metal oxide semiconductor field effect transistor, due to short-channel effects, has become inevitable. Higher ION/IOFF ratios and faster switching rates are quintessential characteristics for nanoelectronics. A field effect diode (FED) is one such device that exhibits greater drive current and low leakages when compared to silicon on insulator technology. Also, the FED fabrication process is compatible with complimentrary metal oxide semiconductor technology. Recently, several approaches have been proposed to tackle the low OFF current problem in FED such as Modified—FED and Side—Contacted FED. The FED structure proposed here is also believed to exhibit lesser short-channel effects, smaller OFF-state current, and higher ON-state current than a regular FED structure. We have explored the possible effects of material variation and work function engineering in our structure. Comprehensive analysis of the proposed device has also been done on some figures of merit such as subthreshold slope, energy-delay product, intrinsic gate delay, etc. thereby making this device suitable for electrostatic-discharge protection. Our numerical investigation promises FED’s efficacy in future logic applications in the nanometre regime.